PolyU develops quantum-tunnelling field-effect transistor to overcome barriers to integrated-circuit chip development

A research team led by Prof. HAO Jianhua, Chair Professor of Materials Physics and Devices and Head of Department of Physics and Materials, in collaboration with researchers from Hong Kong, Beijing and Singapore, has engineered a novel tunnelling field-effect transistor (TFET) utilising two-dimensional (2D) nanomaterials. The breakthrough brings this long-awaited experimental technology closer to commercial reality, offering a fundamental building block for energy-efficient computing and next-generation artificial intelligence (AI) chips.

Integrated circuits (ICs), composed of transistors switching between ON and OFF states, form the foundation of modern computing. Conventional complementary metal–oxide–semiconductor field-effect transistors (MOSFETs) rely on thermionic emission of electrical charges over a barrier, driven by the gating voltage, the minimum of which is just 60 millivolts (mV). However, the notorious Boltzmann limit, or “Boltzmann tyranny”, makes subthreshold swing (SS, a measure of switching barrier) values below 60 mV decade⁻¹ at room temperature a physical impossibility for MOSFETs, putting the brakes on further progress in high-performance electronics.

To solve the performance limitations of previous TFET designs, Prof. Hao’s team created ultra-thin heterostructure of 2D bismuth (Bi) and indium selenide (InSe) alternating layers using pulsed laser deposition (PLD). By exercising precise control over the layer structure at nanoscale, the normally semi-metallic bismuth transforms into a semiconductor in 2D form, creating ideal energy band alignment for charge carriers to tunnel efficiently into InSe through quantum tunnelling mechanism.

The resulting Bi/InSe TFET achieved SS values well below the 60 mV decade⁻¹ thermionic limit across six orders of magnitude of current switching. Operating at room temperature on standard centimetre-scale silicon substrates, the device required a gate-voltage range of only 160 mV—far lower than the 800 mV required by advanced MOSFETs.

Crucially, the device resolved a long-standing challenge in experimental TFETs by delivering a high output current of up to several microamps per micrometre (μA μm⁻¹) alongside an exceptionally high ON/OFF current ratio. High output current is essential for driving multiple downstream logic gates (fan-out), demonstrating diminished circuit-delay, and ensuring compatibility with and even generational upgrade for the existing IC chips.

The study also demonstrates the practical viability of PLD for high-precision, wafer-scale manufacturing of 2D materials appreciated for future transistors with ultra-short channel lengths. Given its seamless integration capability with traditional silicon-based manufacturing processes, this breakthrough provides a scalable roadmap for energy-efficient microchips and specialised hardware powering AI applications.

The research was conducted in collaboration with researchers from the National University of Singapore, The Hong Kong University of Science and Technology, Peking University, and the Singapore University of Technology and Design. The landmark findings have been published in the prestigious international scientific journal Science.

Prof. Hao Jianhua is currently a Member of Photonics Research Institute (PRI), Otto Poon Charitable Foundation Research Institute for Smart Energy (RISE) and Research Institute for Sports Science and Technology (RISports).

Read the full paper: https://www.science.org/doi/10.1126/science.adx6059

Press release: https://www.polyu.edu.hk/rio/news/2026/20260831---polyu-develops-quantum-tunnelling-field-effect-transistor/

 

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