PM Distinguished Seminar - Resistive-Gate Memory: High Density Storage to In-Memory Computing
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Date
18 Sep 2026
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Organiser
Department of Physics and Materials
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Time
15:00 - 16:00
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Venue
HJ302, 3/F, Wing HJ, PolyU Map
Speaker
Prof. Steve CHUNG
Summary
In around 2007, traditional SiO2 gate oxide was replaced by the high-k metal-gate technology of CMOS at the 45 nm generation in production. This HKMG technology is a watershed for the current high-performance CPU, GPU, and MCU and the combination with various memories for applications in smartphone, multimedia, AI, IoT, and automotives.
On the other hand, in terms of embedded memory beyond the HKMG generations, it is essential to develop a technology which needs to be compatible with logic-CMOS high-end processors. First in this talk, a unique structure of resistive-gate memory architecture will be introduced with high speed, low power, and QLC capability. This technology has great potential for embedded applications and may compete with floating-gate NOR/NAND, in a near future.
Also, in the development of AI, deep learning has been built mainly within the cloud-based domain accelerated by TPUs and GPUs with more than hundreds of watts of power. In contrast, an edge inference research received much more attention on high energy efficiency. So, in this talk, fundamentals on developing CIM(compute-In-Memory) across the HKMG generations will be introduced. Then, examples of CIM macros based on the Resistive-gate architecture will be demonstrated.
Keynote Speaker
Prof. Steve CHUNG
Life Chair Professor
Department of Electronics and Electrical Engineering
National Yang Ming Chiao Tung University
Steve Chung received his Ph. D. from University of Illinois at Urbana-Champaign. He is a Life Chair professor of NYCU (former NCTU) with past administrative position in managing International Office, a visiting prof. to both Stanford and UC-Merced, taught graduate courses, in 2021 and 2008 respectively. His research includes the two main streams of the semiconductor IC industry: nanoscale CMOS technology and flash memory. He has authored more than 350 journal and major international conference papers, holds about 50 patents. He was the first speaker at VLSI (1995) among Taiwan authors and has close to 40 times presentation experience at IEDM and VLSI. He is an IEEE Life Fellow, US NAI Fellow. He has made significant contributions to the semiconductor community through extensive service in the IEEE, 12 years of EDS nanoscale CMOS technology and flash memory, Chair of Asia-Pacific regional chapter, a member of the IEEE Fellow Committee, an IEEE Distinguished Lecturer, journal editor, conference chair, and keynote speaker. He also received the nanoscale CMOS technology and flash memory
